Crosstalk between differential pairs of conductors disposed in packaging for routing signals between a printed circuit board and a semiconductor device or chip can be a serious problem. When of sufficient magnitude, crosstalk can inhibit or even prevent the accurate transmission of signals to and from an integrated circuit device, especially in high-speed data communication applications such as high-speed routers and the like. As devices become smaller, and signal conductor pairs become more closely spaced, the problems caused by crosstalk increase.
One prior art solution for tackling the various problems presented by crosstalk is to increase the spacing between differential conductor pairs. Such a solution, however, requires additional package layers and cost.
Another prior art solution for dealing with crosstalk is to employ impedance excursions with varying spacing between differential conductor pairs while routing between an integrated circuit bump pitch to a printed circuit board ball pitch. This solution requires advanced non-linear design capabilities and is expensive and time-consuming to design properly.
Still another prior art solution for minimizing the impact of crosstalk is to increase the number of guard traces in a package. This approach, however, requires additional space, added guard traces, or a reduced number of signals that a given package layer can support. Adding package layers increases cost.
Adding to the complexities of designing packages with reduced crosstalk is the fact that parasitic capacitance effects introduced by solder bump and solder ball interconnects on such packages are notoriously difficult to model.
What is needed is a means of providing reduced crosstalk while increasing signal routing density, with crosstalk preferably being less than 1% (or −40 dB) in respect of data signals transmitted over signal conductor pairs. What is also needed is a means of providing optimum spacing between differential conductor pairs that results in constant impedance while routing between the varying pitch requirements of an integrated circuit and a printed circuit board.
Various patents containing subject matter relating directly or indirectly to the field of the present invention include, but are not limited to, the following:
U.S. Pat. No. 7,043,706 to Brist et al. for “Conductor trace design to reduce common mode cross-talk and timing skew,” May 9, 2006.
U.S. Pat. No. 6,304,700 to Brand et al. for “Device for transmitting high-frequency communication signals and method for manufacturing the device,” Oct. 16, 2001.
U.S. Pat. No. 5,418,504 to Nottenburg for “Transmission line,” May 23, 1995.
U.S. Pat. No. 6,951,806 to Schweikert et al. for “Metal region for reduction of capacitive coupling between signal lines,” Oct. 4, 2005.
U.S. Pat. No. 6,166,440 to Yang for “Interconnection for preventing signal interference in a semiconductor device,” Dec. 26, 2000.
U.S. Pat. No. 7,002,253 to Katsura et al. for “Semiconductor device and design method thereof,” Feb. 21, 2006.
U.S. Pat. No. 6,352,914 to Ball et al. for “Interleaved signal trace routing,” Mar. 5, 2002.
U.S. Pat. No. 6,559,484 to Lee et al. for “Embedded enclosure for effective electromagnetic radiation reduction,” May 6, 2003.
U.S. Pat. No. 6,265,672 to Eum et al. for “Multiple layer module structure for printed circuit board,” Jul. 24, 2001.
U.S. Pat. No. 5,585,664 to Ito for “Semiconductor integrated circuit device,” Dec. 17,1996.
U.S. Pat. No. 7,030,455 to Gamand et al. for “Integrated electromagnetic shielding device,” Apr. 18, 2006.
U.S. Pat. No. 5,027,088 to Shimizu et al. for “Signal wiring board,” Jun. 25, 1991.
U.S. Pat. No. 6,590,466 to Lin et al. for “Circuit board having shielding planes with varied void opening patterns for controlling the impedance and the transmission time of differential transmission lines,” Jul. 8, 2003.
U.S. Pat. No. 6,767,252 to McGrath et al. for “High speed differential signal edge card connector and circuit board layouts therefor,” Jul. 27, 2004.
U.S. Pat. No. 6,444,922 to Kwong for “Zero cross-talk signal line design,” Sep. 3, 2002.
U.S. Pat. No. 5,828,555 to Itoh for “Multilayer printed circuit board and high-frequency circuit device using the same,” Oct. 27, 1998.
U.S. Pat. No. 5,677,515 to Sel et al. for “Shielded multilayer printed wiring board, high frequency, high isolation,” Oct. 14, 1997.
The dates of the foregoing publications may correspond to any one of priority dates, filing dates, publication dates and issue dates. Listing of the above patents and patent applications in this background section is not, and shall not be construed as, an admission by the applicants or their counsel that one or more publications from the above list constitutes prior art in respect of the applicant's various inventions. All printed publications and patents referenced herein are hereby incorporated by referenced herein, each in its respective entirety.
Upon having read and understood the Summary, Detailed Descriptions and Claims set forth below, those skilled in the art will appreciate that at least some of the systems, devices, components and methods disclosed in the printed publications listed herein may be modified advantageously in accordance with the teachings of the various embodiments of the present invention.